A semiconductor integrated circuit 100, shown in FIG. 1, normally includes an input stage 1 adapted for acquiring and regenerating external input signals 4. The integrated circuit 100 also includes generic internal circuitry 2 and an output stage 3 adapted to drive external signal lines 5 to which there is associated a load 6.
The output signal from such an output stage 3 is in general variable between different logic levels in relatively short times. For example, referring to FIG. 1, the output signal 5 switches between the reference voltage Gnd (0 V) and the supply voltage Vcc of the integrated circuit, typically equal to 5 V in the case of the CMOS logic family. The output stage 3 will therefore supply high currents in short times. Such currents can disturb the internal circuitry 2 and the input stage 1 of the integrated circuit. These disturbances could be interpreted, in the case of memory integrated circuits, as logic state transitions on the address signal bus 4, for the following reasons.
The terminals of the supply voltage, the reference voltage and the input/output signals provided on the semiconductor chip of the integrated circuit are respectively connected to a supply voltage line, a reference voltage line and input/output lines external to the chip by means of bonding wires. These bonding wires introduce parasitic inductances contributing to the creation of closed paths between the different stages, as shown in FIG. 2.
In this figure, Vcc and Gnd are the supply voltage line and the reference voltage line external to the integrated circuit chip. The stages 1 and 2 of FIG. 1 (of which only the former is shown in FIG. 2) are supplied by a first internal supply voltage Vcc1, connected to Vcc by means of a first metal wire L1 having a parasitic inductance L1. The reference voltage of these stages is GND1 that is connected to the external reference voltage Gnd by means of a second metal wire L3 having a parasitic inductance L3. The output stage 3 is supplied by a second internal supply voltage Vcc2 which is connected to the external supply voltage Vcc by means of a third metal wire L2 having a parasitic inductance L2, distinct from the first metal wire L1. The internal reference voltage Gnd2 for the output stage 3 is connected to the external reference voltage Gnd by means of a fourth metal wire L4 having a parasitic inductance L4, distinct from the second metal wire L3.
IN and OUT respectively are the terminals external to the integrated circuit for the connection of the input and output signals. These terminals are connected to the input stage 1 and to the output stage 3 through metal wires Lin and Lout having respective parasitic inductances Lin and Lout. Cload is a capacitive load. The input stage 1 generally comprises pull-up and pull-down transistors P1 and N1, while the output stage 3 comprises pull-up and pull-down transistors P2 and N2.
Referring to FIG. 3, the physical structure of the output stage 3 of FIG. 2 is shown. It can be noted that the P-channel pull-up transistor P2 is obtained by introducing into the P type substrate 7 donor atoms, so as to form an N type well 8. A subsequent introduction of acceptor atoms forms the drain and source regions 9, 10. The N type well 8 is biased at Vcc2. The drain and source regions 11, 12 of the pull-down N-channel transistor N2 are obtained by introducing donor atoms directly into the substrate 7 or, in the alternative case that transistor N2 is to have a particular threshold voltage, in a further P type well 13 formed in substrate 7 (twin-well process), with the substrate 7 being normally lightly doped.
C2 is the capacitance of the junction between the N type well 8 and the P type substrate 7, i.e. the capacitance between Vcc2 and Gnd1. C1 shown in FIG. 2 is the capacitance associated with the junction between the P type substrate 7 and one or more N type wells similar to the well 8 for the P-channel transistors of the input stages 1 and the circuitry 2, i.e. the capacitance coupling Vcc1 and Gnd1. Rsub is the resistance of the substrate 7.
If the potential of node Vcc2 fluctuates at low frequencies, the inductances of the metal wires are short circuits and the path .gamma. formed by L1 and L2 is predominant. This is so since .gamma. is the sole direct path between Vcc2 and Vcc1. At higher frequencies corresponding to the switching frequency of the output buffers, path .beta. formed by capacitances C1 and C2 is predominant. In both cases, however, the disturbance on the input stage is limited.
If in contrast node Gnd2 fluctuates these fluctuations affect through the resistive path .alpha., the input circuitry, due to the small equivalent resistance Rsub between Gnd2 and Gnd1. It is common practice to try to resolve this problem by introducing latches for the data and increasing the noise margin of the input buffers.
To eliminate the path .alpha. through the substrate resistance Rsub between Gnd2 and Gnd1, a known technique provides for using a so-called triple-well manufacturing process to form the output stage 3, as depicted in FIGS. 4 and 5. From FIG. 4 it is noted that in a triple-well structure the transistor N2 is formed inside a P type well 130, that in turn is formed inside an N type well 140 formed in the P type substrate 7.
Referring to FIG. 5, the use of the triple-well structure allows for eliminating, at least at low frequencies, the path .alpha.. In fact, connecting the P type well 130 to Gnd2 and the N type well 140 to Vcc2, the junctions of the P type well 130/N type well 140 and N type well 140/P type substrate 7 are reverse biased.
As however shown in FIG. 4, such junctions have associated therewith two further parasitic capacitances C21, between the N type well 140 and the P type substrate 7, and C22 between the P type well 130 and the N type well 140. These capacitances, even if they contribute to a better filtering of noise with respect to approaches not using the triple-well structure, still allow switching noise to be transferred to the input circuitry at high frequencies. This is more true the closer the cutoff frequency of the high-pass filter associated with C21 and C22 to the signal frequency, and thus the larger the capacitances C21 and C22.